Time: 2020-05-28 www.sdyserver.cn
Intel's breasts: DDR5, PCIe 5.0 See you next year!

For various reasons, Intel ’s product planning has been adjusted very frequently in the past two years, and the roadmap has frequently changed, whether it is consumer or enterprise.


In communication with investors recently, Intel ’s Director of Public Relations Trey Campbell promised that the next-generation Xeon server platform code-named Ice Lake-SP will be released by the end of the second quarter of this year (at the latest until the end of June), and sometime next year Will bring Sapphire Rapids.








Ice Lake-SP will use the same 10nm process as the mobile Ice Lake-U / Y series, Sunny Cove CPU architecture, and replace the new LGA4189 package interface. The number and frequency of cores are temporarily unknown (it is said that up to 38 cores), but will be introduced The PCIe 4.0 bus has a maximum of 64, and the memory continues to support DDR4, but will expand from six channels to eight channels, and the frequency is also expected to increase to 3200MHz.


Sapphire Rapids will use an enhanced version of 10nm + technology to upgrade to a newer generation of Willow Cove CPU architecture, which is said to be up to 56 cores and 112 threads, and is the first to introduce DDR5 memory and PCIe 5.0 bus. 50.


On the desktop, it is said that Intel Alder Lake (12th generation Core) will also introduce DDR5 memory, and AMD is expected to wait until the Zen 4 architecture.


Interestingly, Ice Lake-SP actually planned to have a Xeon platform Cooper Lake, which is still a 14nm process, and the architecture and technical specifications have not changed much. As long as machine learning is enhanced, the interface is also the new LGA4189.


Such a design cannot naturally attract OEM customers, and Intel also has to reduce its size, only for the four-way and eight-way markets, and this market is very very small.